Z80.h

00001 // Note that the Z80 can actually address 64k of ports, not just 256! For most
00002 //  applications you probably only want to pay attention to the low 8 bits, though,
00003 //  because most code is not written with this in mind.
00004 
00005 #ifndef __CPU_Z80_H__
00006 #define __CPU_Z80_H__
00007 
00008 #include "mempage.h"
00009 #include "cpu/cycle.h"
00010 
00011 #ifdef OE_ENDIAN_LITTLE
00012 union CPU_Z80_reg16 {
00013     uint16 val;
00014     struct {
00015         uint8 H;
00016         uint8 L;
00017     };
00018 };
00019 #else
00020 union CPU_Z80_reg16 {
00021     uint16 val;
00022     struct {
00023         uint8 L;
00024         uint8 H;
00025     };
00026 };
00027 #endif
00028 
00029 enum { CPU_Z80_AF, CPU_Z80_BC, CPU_Z80_DE, CPU_Z80_HL };
00030 
00031 struct CPU_Z80_STATE {
00032 };
00033 
00034 struct CPU_Z80_DEBUG_STATE {
00035 };
00036 
00037 struct CPU_Z80_ins {
00038 };
00039 
00040 class CPU_Z80 {
00041   public:
00042     void init();                            // 1) Call this on init
00043 //  void set_mode(int mode, int support);   // 2) Then call this to set the mode. Arguments 1: M65C02_MODE_xxxx for processor type. Argument 2 should be 0 to turn off nonstandard (undocumented) opcode support, anything else to turn it on.
00044                                             // 3) Make sure your memory is setup before you do step 4!
00045     void reset();                           // 4) Then call this to start the emulator. It will jump to the location contained at RESETVEC (0xFFFC)
00046                                             // Note that you MUST do all this before you use the processor, even restoring a state!
00047     CPU_CYCLE_COUNT cycles;
00048     void cycle(dword numleft);              // Do cycles!
00049 
00050     void save_state(CPU_Z80_STATE *foo);        // Save the state!
00051     void restore_state(CPU_Z80_STATE *foo); // Restore the state!
00052 
00053     // Debug support
00054     void set_debug_mode(uint16 mode);       // Set the debug mode!
00055     char *debug_str(CPU_Z80_DEBUG_STATE *s);    // Returns a string containing debug info dump
00056     CPU_DBGINF dbg;
00057     CPU_Z80_DEBUG_STATE dbg_iop_state;  // Holds the debug state on illegal op
00058 
00059     // Memory system
00060     oe_pagetable mem;
00061 
00062     // External interfaces
00063     uint16 HLT;         // If the CPU is HLT'd
00064     uint16 IRQ;         // IRQ request
00065     uint16 NMI;         // NMI request
00066 
00067     BYTE (*read_port)(CPU_Z80 *ref, uint16 port);                   // Reads from a port
00068     void (*write_port)(CPU_Z80 *ref, uint16 portl, uint8 val);      // Writes to a port
00069 
00070   private:
00071     uint16 curbank;             // Current register bank being used
00072     uint16 interrupt_mode;      // Interrupt mode 0-2
00073     uint8 interrupt_data[12];   // Interrupt data buffer for modes 0 and 2
00074 
00075     uint16 *ireg;       // Current index register used
00076     uint16 *reg16_1;    // 16-bit register #1 used
00077     uint16 *reg16_2;    // 16-bit register #2 used
00078 
00079     uint8 *reg8_1;      // 8-bit register #1 used
00080     uint8 *reg8_2;      // 8-bit register #2 used
00081 
00082     uint16 regaddr;     // Address reg
00083 
00084     // Registers
00085     CPU_Z80_reg16 regs[2][4];       // 2 banks of AF, BC, DE, HL
00086     uint8 IFF1;
00087     uint8 IFF2;
00088 
00089 #ifdef OE_ENDIAN_LITTLE
00090         union{                          // IX
00091         uint16 IX;
00092         struct {
00093             uint8 IXh;
00094             uint8 IXl;
00095         };
00096     };
00097     union {                         // IY
00098         uint16 IY;
00099         struct {
00100             uint8 IYh;
00101             uint8 IYl;
00102         };
00103     };
00104     union {                         // PC
00105         uint16 PC;
00106         struct {
00107             uint8 PCh;
00108             uint8 PCl;
00109         };
00110     };
00111     union {                         // IR
00112         uint16 IR;
00113         struct {
00114             uint8 I;
00115             uint8 R;
00116         };
00117     };
00118     union {                         // SP
00119         uint16 SP;
00120         struct {
00121             uint8 SPh;
00122             uint8 SPl;
00123         };
00124     };
00125 #else
00126     union {                         // IX
00127         uint16 IX;
00128         struct {
00129             uint8 IXl;
00130             uint8 IXh;
00131         };
00132     };
00133     union {                         // IY
00134         uint16 IY;
00135         struct {
00136             uint8 IYl;
00137             uint8 IYh;
00138         };
00139     };
00140     union {                         // PC
00141         uint16 PC;
00142         struct {
00143             uint8 PCl;
00144             uint8 PCh;
00145         };
00146     };
00147     union {                         // IR
00148         uint16 IR;
00149         struct {
00150             uint8 R;
00151             uint8 I;
00152         };
00153     };
00154     union {                         // SP
00155         uint16 SP;
00156         struct {
00157             uint8 SPl;
00158             uint8 SPh;
00159         };
00160     };
00161 #endif
00162     // Functions
00163 
00164     void setjumptable(int ins, int mode);   // Sets instruction jump table info
00165     CPU_Z80_ins iinf[4][256];   // Various timing, addressing, etc. information for the instructions
00166 
00167     void (CPU_Z80::*inst[4][256])(void);        // Instruction jump table
00168 
00169     // Debug stuff
00170     void IllegalOpcode();           // Illegal operation.
00171     
00172     // Z80 Instructions
00173 //  void ();                        // 
00174 };
00175 
00176 #endif

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