RCA1802.cpp

//  Ahh, the RCA 1802 COSMAC 8-bit processor. Used in the RCA Studio II video game system, the
// Voyager, Galileo, and other spacecraft, and some nuclear warheads. It has a cool, RISC-like
// design, despite being originally designed in 1976.

//  It was also used in several early computers, such as the COSMAC ELF. It is fully binary
// compatible with the earlier RCA 1801.

// TODO: Add cycle() and DMA support

#include "openem.h"
#include "cpu/debug/cpudbg.h"
#include "cpu/RCA1802/RCA1802.h"

#include <stdlib.h>
#include <stdio.h>
#include <string.h>


#define RCAPX_NONE      0
#define RCAPX_68        1
#define RCACR_STOPPED   0
#define RCACR_RUNNING   1

// The follow few functions are dummies for memory, Q, and N read/writes
BYTE dummyefr(CPU_RCA1802 *ref, byte num)
{
    return 0;
}

void dummywq(CPU_RCA1802 *ref, byte oldval, byte newval)
{
}

BYTE dummyrn(CPU_RCA1802 *ref, byte d)
{
    return 0;
}

void dummywn(CPU_RCA1802 *ref, byte d, byte c)
{
}

// DMA!
void CPU_RCA1802::DMA_OUT(void *dest, uint32 num)
{
    if (num == 0) return;
#ifdef DEBUG_CPU_RCA1802
    CPU_DEBUG_STATE *cds;
    CPU_RCA1802_DEBUG_STATE *mds;
    if (dbg.debug_on) {
        dbg.list.add_to_end();
        cds = dbg.list.getlast();
        mds = (CPU_RCA1802_DEBUG_STATE *)malloc(sizeof(CPU_RCA1802_DEBUG_STATE));
        cds->cstate = (void *)mds;
        mds->flag = CPU_STATE_DMA;
        save_state(&mds->s);
    }
#endif
    cycles.overage += num;
    uint8 *ptr = (uint8 *)dest;
    for (uint32 i = 0; i < num; i++) {
        *ptr = mem.read_mem8(this,R[0]);
        R[0]++;
        ptr++;
    }
    IDL = 0;
}

void CPU_RCA1802::DMA_IN(void *src, uint32 num)
{
    if (num == 0) return;
#ifdef DEBUG_CPU_RCA1802
    CPU_DEBUG_STATE *cds;
    CPU_RCA1802_DEBUG_STATE *mds;
    if (dbg.debug_on) {
        dbg.list.add_to_end();
        cds = dbg.list.getlast();
        mds = (CPU_RCA1802_DEBUG_STATE *)malloc(sizeof(CPU_RCA1802_DEBUG_STATE));
        cds->cstate = (void *)mds;
        mds->flag = CPU_STATE_DMA;
        save_state(&mds->s);
    }
#endif
    cycles.overage += num;
    uint8 *ptr = (uint8 *)src;
    for (uint32 i = 0; i < num; i++) {
        mem.write_mem8(this,R[0],*ptr);
        R[0]++;
        ptr++;
    }
    IDL = 0;
}


// Execute!
void CPU_RCA1802::cycle(uint32 num)
{
    cycles.left =  num;
    cycles.since_call = 0;

#ifdef DEBUG_CPU_RCA1802
    CPU_DEBUG_STATE *cds;
    CPU_RCA1802_DEBUG_STATE *mds;
    if (dbg.debug_on) {
        dbg.list.add_to_end();
        cds = dbg.list.getlast();
        mds = (CPU_RCA1802_DEBUG_STATE *)malloc(sizeof(CPU_RCA1802_DEBUG_STATE));
        cds->cstate = (void *)mds;
        mds->flag = CPU_STATE_STARTEDCYCLING;
        save_state(&mds->s);
    }
#endif

    if (num == 0) return;

    // Deal with a cycle overage
    if (cycles.overage) {
        if (cycles.overage > IRQ) { IRQ = 0; }
        else IRQ -= cycles.overage;
        if (cycles.overage >= cycles.left) {
            cycles.overage -= cycles.left;
            cycles.since_call += cycles.left;
            cycles.total += cycles.left;
            cycles.left = 0;
            return;
        }
        else {
            cycles.left -= cycles.overage;
            cycles.since_call += cycles.overage;
            cycles.total += cycles.overage;
            cycles.overage = 0;
        }
    }

    // Start executing
    do {
        // Check to see if there's an IRQ
        if (IRQ && MIE && (XIE || CIE)) {
            MIE = 0;                    // Disable external interrupts
            IDL = false;                // Take us out of idle state if we're in it
            T = (X << 4) | (P & 0x0F);  // Store X and P into T
            X = 2;                      // Set X to interrupt default
            P = 1;                      // Set P to interrupt default
#ifdef DEBUG_CPU_RCA1802
            if (dbg.debug_on) {
                dbg.list.add_to_end();
                cds = dbg.list.getlast();
                mds = (CPU_RCA1802_DEBUG_STATE *)malloc(sizeof(CPU_RCA1802_DEBUG_STATE));
                cds->cstate = (void *)mds;
                mds->flag = CPU_STATE_IRQ_EXECUTED;
                save_state(&mds->s);
            }
#endif
        }
        if (IDL) {      // Now if we're idle still...
            cycles.overage = 0;
            cycles.total += cycles.left;
            cycles.since_call += cycles.left;
            cycles.left = 0;
            cycles.curins = 0;
#ifdef DEBUG_CPU_RCA1802
            if (dbg.debug_on) {
                dbg.list.add_to_end();
                cds = dbg.list.getlast();
                mds = (CPU_RCA1802_DEBUG_STATE *)malloc(sizeof(CPU_RCA1802_DEBUG_STATE));
                cds->cstate = (void *)mds;
                mds->flag = CPU_STATE_IDLING;
                save_state(&mds->s);
            }
#endif
        }
        else {              // Execute an instruction
            curins = mem.read_mem8(this,R[P]);      // Get the current instruction
            N = iinf[RCAPX_NONE][curins].regnum;                // Set N
#ifdef DEBUG_CPU_RCA1802
            if (dbg.debug_on) {
                dbg.list.add_to_end();
                cds = dbg.list.getlast();
                mds = (CPU_RCA1802_DEBUG_STATE *)malloc(sizeof(CPU_RCA1802_DEBUG_STATE));
                cds->cstate = (void *)mds;
                mds->flag = CPU_STATE_RUNNING;
                save_state(&mds->s);
                mds->nextmem[0] = mem.read_mem8(this,R[P]);
                mds->nextmem[1] = mem.read_mem8(this,R[P]+1);
                mds->nextmem[2] = mem.read_mem8(this,R[P]+2);
                mds->nextmem[3] = mem.read_mem8(this,R[P]+3);
                mds->nextmem[4] = mem.read_mem8(this,R[P]+4);
            }
#endif
            R[P]++;                                 // Increment the PC
            (this->*inst[RCAPX_NONE][curins])();                // Call an instruction
            cycles.curins = iinf[RCAPX_NONE][curins].cycl;
        }
        if (IRQ) {
            if (cycles.curins < reset_IRQ)
                IRQ -= cycles.curins;
            else
                IRQ = 0;
        }
        
        if (cycles.left == 0) break;
        if (cycles.curins >= cycles.left) {
            cycles.overage = cycles.curins - cycles.left;
            cycles.total += cycles.left;
            cycles.since_call += cycles.left;
            cycles.left = 0;
        }
        else {
            cycles.left -= cycles.curins;
            cycles.total += cycles.curins;
            cycles.since_call += cycles.curins;
        }
    } while(cycles.left);
}

// Save the state!
void CPU_RCA1802::save_state(CPU_RCA1802_STATE *foo)
{
    foo->Q = Q;
    foo->IDL = IDL;
    foo->IRQ = IRQ;
    foo->cycles = cycles;
    for (int i = 0; i < 16; i++) { foo->R[i] = R[i]; }
    foo->D = D;
    foo->B = B;
    foo->DF = DF;
    foo->P = P;
    foo->X = X;
    foo->XIE = XIE;
    foo->MIE = MIE;
    foo->CIE = CIE;
    foo->counter = counter;
    foo->N = N;
    foo->T = T;
}

// Restore the state!
void CPU_RCA1802::restore_state(CPU_RCA1802_STATE *foo)
{
    Q = foo->Q;
    IDL = foo->IDL;
    IRQ = foo->IRQ;
    cycles = foo->cycles;
    for (int i = 0; i < 16; i++) { R[i] = foo->R[i]; }
    D = foo->D;
    B = foo->B;
    DF = foo->DF;
    P = foo->P;
    X = foo->X;
    XIE = foo->XIE;
    MIE = foo->MIE;
    CIE = foo->CIE;
    counter = foo->counter;
    N = foo->N;
    T = foo->T;
}

// Set the debug mode!
void CPU_RCA1802::set_debug_mode(uint16 mode)
{
    dbg.mode = mode;
}

// SHIFT LOGIC IS SUSPECT
// See instructions below for more info
CPU_RCA1802::CPU_RCA1802(void)
{
    read_EF = dummyefr;
    write_Q = dummywq;
    read_N = dummyrn;
    write_N = dummywn;
}


void CPU_RCA1802::init(void)
{
    curprefix = RCAPX_NONE;
    support_1806 = 0;
    IDL = false;
    IRQ = 0;
    dbg.mode = CPU_DEBUG_IOP_IGNORE;
    dbg.iop_exit = 0;
    dbg.list.clear();
    cycles.overage = cycles.curins = cycles.left = cycles.since_call = cycles.total = 0;
    mem.init();
    for (int i = 0; i < 256; i++) {
        setjumptable(i);
    }
}

void CPU_RCA1802::set_mode(uint32 mode)
{
    switch(mode) {
    case RCA1802_MODE_1802:
        support_1806 = 0;       
        break;
    case RCA1802_MODE_1803:
        support_1806 = 1;
        break;
    }
    if (support_1806) {
        inst[RCAPX_NONE][0x68] = &CPU_RCA1802::Prefix;
        iinf[RCAPX_NONE][0x68].cycl = 0;
    }
    else {
        inst[RCAPX_NONE][0x68] = &CPU_RCA1802::IllegalOp;
        iinf[RCAPX_NONE][0x68].cycl = 1;
    }
}

// regnum, cycl
void CPU_RCA1802::setjumptable(int ins)
{
    int i;
    inst[RCAPX_NONE][ins] = &CPU_RCA1802::IllegalOp;
    iinf[RCAPX_NONE][ins].cycl = 1;
    iinf[RCAPX_NONE][ins].regnum = 1;
    inst[1][ins] = &CPU_RCA1802::IllegalOp;
    iinf[1][ins].cycl = 1;
    iinf[1][ins].regnum = 1;
    switch(ins&0xF0) {
        case 0x00:  //-0x0F LD by N         Memory pointed to by R(N) is loaded into D.
            for (i = 1; i < 16; i++) {
                inst[RCAPX_NONE][i] = &CPU_RCA1802::LDN;
                iinf[RCAPX_NONE][i].regnum = i;
                iinf[RCAPX_NONE][i].cycl = 2;
            }
            inst[RCAPX_NONE][0] = &CPU_RCA1802::iIDL;
            iinf[RCAPX_NONE][0].cycl = 1;
            break;
        case 0x10:  //-0x1F INC REG N
            for (i = 0; i < 16; i++) {
                inst[RCAPX_NONE][i+0x10] = &CPU_RCA1802::INC;
                iinf[RCAPX_NONE][i+0x10].regnum = i;
                iinf[RCAPX_NONE][i+0x10].cycl = 2;
            }
            break;
        case 0x20: //-0x2F DEC REG N
            for (i = 0; i < 16; i++) {
                inst[RCAPX_NONE][i+0x20] = &CPU_RCA1802::DEC;
                iinf[RCAPX_NONE][i+0x20].regnum = i;
                iinf[RCAPX_NONE][i+0x20].cycl = 2;
                inst[RCAPX_68][0x20+i] = &CPU_RCA1802::DBNZ;
                iinf[RCAPX_68][0x20+i].regnum = i;
                iinf[RCAPX_68][0x20+i].cycl = 5;
            }
            break;
        case 0x40:  //-0x4F LD Advance      Memory pointed to by R(N) is loaded into D, R(N)+1. DF is NOT changed.
            for (i = 0; i < 16; i++) {
                inst[RCAPX_NONE][0x40+i] = &CPU_RCA1802::LDA;
                iinf[RCAPX_NONE][0x40+i].regnum = i;
                iinf[RCAPX_NONE][0x40+i].cycl = 2;
            }
            break;
        case 0x50:  //-0x5F STR via N       Memory pointed to by R(N) is set to D
            for (i = 0; i < 16; i++) {
                inst[RCAPX_NONE][0x50+i] = &CPU_RCA1802::STR;
                iinf[RCAPX_NONE][0x50+i].regnum = i;
                iinf[RCAPX_NONE][0x50+i].cycl = 2;
            }
            break;
        case 0x60:  //-0x6F INX and OUTX
            for (i = 1; i < 8; i++) {
                inst[RCAPX_NONE][0x60+i] = &CPU_RCA1802::OUTX;
                iinf[RCAPX_NONE][0x60+i].regnum = i;
                iinf[RCAPX_NONE][0x60+i].cycl = 2;
                inst[RCAPX_68][0x60+i] = &CPU_RCA1802::RLXA;
                iinf[RCAPX_68][0x60+i].regnum = i;
                iinf[RCAPX_68][0x60+i].cycl = 5;
            }
            for (i = 9; i < 16; i++) {
                inst[RCAPX_NONE][0x60+i] = &CPU_RCA1802::INX;
                iinf[RCAPX_NONE][0x60+i].regnum = i - 8;
                iinf[RCAPX_NONE][0x60+i].cycl = 2;
            }
            break;
        case 0x80:  //-0x8F GLO N           D = low byte of N
            for (i = 0; i < 16; i++) {
                inst[RCAPX_NONE][0x80+i] = &CPU_RCA1802::GLO;
                iinf[RCAPX_NONE][0x80+i].regnum = i;
                iinf[RCAPX_NONE][0x80+i].cycl = 2;
                inst[RCAPX_68][0x80+i] = &CPU_RCA1802::SCAL;
                iinf[RCAPX_68][0x80+i].regnum = i;
                iinf[RCAPX_68][0x80+i].cycl = 10;
            }
            break;
        case 0x90:  //-0x9F GHI N           D = high byte of N
            for (i = 0; i < 16; i++) {
                inst[RCAPX_NONE][0x90+i] = &CPU_RCA1802::GHI;
                iinf[RCAPX_NONE][0x90+i].regnum = i;
                iinf[RCAPX_NONE][0x90+i].cycl = 2;
                inst[RCAPX_68][0x90+i] = &CPU_RCA1802::SRET;
                iinf[RCAPX_68][0x90+i].regnum = i;
                iinf[RCAPX_68][0x90+i].cycl = 8;
            }
            break;
        case 0xA0:  //-0xAF PLO N           low byte of N = D
            for (i = 0; i < 16; i++) {
                inst[RCAPX_NONE][0xA0+i] = &CPU_RCA1802::PLO;
                iinf[RCAPX_NONE][0xA0+i].regnum = i;
                iinf[RCAPX_NONE][0xA0+i].cycl = 2;
                inst[RCAPX_68][0xA0+i] = &CPU_RCA1802::RSXD;
                iinf[RCAPX_68][0xA0+i].regnum = i;
                iinf[RCAPX_68][0xA0+i].cycl = 5;
            }
            break;
        case 0xB0:  //-0xBF PHI N           high byte of N = D
            for (i = 0; i < 16; i++) {
                inst[RCAPX_NONE][0xB0+i] = &CPU_RCA1802::PHI;
                iinf[RCAPX_NONE][0xB0+i].regnum = i;
                iinf[RCAPX_NONE][0xB0+i].cycl = 2;
                inst[RCAPX_68][0xB0+i] = &CPU_RCA1802::RNX;
                iinf[RCAPX_68][0xB0+i].regnum = i;
                iinf[RCAPX_68][0xB0+i].cycl = 4;
            }
            break;
        case 0xC0:  // 0x68 prefix RLDI
            for (i = 0; i < 16; i++) {
                inst[RCAPX_68][0xC0+i] = &CPU_RCA1802::RLDI;
                iinf[RCAPX_68][0xC0+i].regnum = i;
                iinf[RCAPX_68][0xC0+i].cycl = 5;
            }
            break;
        case 0xD0:  //-0xDF SEP N           Set P = N
            for (i = 0; i < 16; i++) {
                inst[RCAPX_NONE][0xD0+i] = &CPU_RCA1802::SEP;
                iinf[RCAPX_NONE][0xD0+i].regnum = i;
                iinf[RCAPX_NONE][0xD0+i].cycl = 2;
            }
            break;
        case 0xE0:  //-0xDF SEX N           Set X = N
            for (i = 0; i < 16; i++) {
                inst[RCAPX_NONE][0xE0+i] = &CPU_RCA1802::SEX;
                iinf[RCAPX_NONE][0xE0+i].regnum = i;
                iinf[RCAPX_NONE][0xE0+i].cycl = 2;
            }
            break;
    }
    switch(ins) {
        case 0x00:  // STPC
            inst[RCAPX_68][ins] = &CPU_RCA1802::STPC;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x01:  // DTC
            inst[RCAPX_68][ins] = &CPU_RCA1802::DTC;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x02:  // SPM2
            inst[RCAPX_68][ins] = &CPU_RCA1802::SPM2;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x03:  // SCM2
            inst[RCAPX_68][ins] = &CPU_RCA1802::SCM2;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x04:  // SPM1
            inst[RCAPX_68][ins] = &CPU_RCA1802::SPM1;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x05:  // SCM1
            inst[RCAPX_68][ins] = &CPU_RCA1802::SCM1;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x06:  // LDC
            inst[RCAPX_68][ins] = &CPU_RCA1802::LDC;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x07:  // STM
            inst[RCAPX_68][ins] = &CPU_RCA1802::STM;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x08:  // GEC
            inst[RCAPX_68][ins] = &CPU_RCA1802::GEC;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x09:  // ETQ
            inst[RCAPX_68][ins] = &CPU_RCA1802::ETQ;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x0A:  // XIE
            inst[RCAPX_68][ins] = &CPU_RCA1802::sXIE;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x0B:  // XID
            inst[RCAPX_68][ins] = &CPU_RCA1802::sXID;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x0C:  // CIE
            inst[RCAPX_68][ins] = &CPU_RCA1802::sCIE;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x0D:  // CID
            inst[RCAPX_68][ins] = &CPU_RCA1802::sCID;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x30:  // BR
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BR;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x31:  // BQ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BQ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x32:  // BZ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BZ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x33:  // BDF
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BDF;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x34:  // B1
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BX;
            iinf[RCAPX_NONE][ins].cycl = 2;
            iinf[RCAPX_NONE][ins].regnum = 1;
            break;
        case 0x35:  // B2
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BX;
            iinf[RCAPX_NONE][ins].cycl = 2;
            iinf[RCAPX_NONE][ins].regnum = 2;
            break;
        case 0x36:  // B3
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BX;
            iinf[RCAPX_NONE][ins].cycl = 2;
            iinf[RCAPX_NONE][ins].regnum = 3;
            break;
        case 0x37:  // B4
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BX;
            iinf[RCAPX_NONE][ins].cycl = 2;
            iinf[RCAPX_NONE][ins].regnum = 4;
            break;
        case 0x38:  // NBR also SKP
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::NBR;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x39:  // BNQ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BNQ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x3A:  // BNZ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BNZ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x3B:  // BNF
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BNF;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x3C:  // BN1
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BNX;
            iinf[RCAPX_NONE][ins].cycl = 2;
            iinf[RCAPX_NONE][ins].regnum = 1;
            break;
        case 0x3D:  // BN2
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BNX;
            iinf[RCAPX_NONE][ins].cycl = 2;
            iinf[RCAPX_NONE][ins].regnum = 2;
            break;
        case 0x3E:  // BN3, BCI
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BNX;
            iinf[RCAPX_NONE][ins].cycl = 2;
            iinf[RCAPX_NONE][ins].regnum = 3;
            inst[RCAPX_68][ins] = &CPU_RCA1802::BCI;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x3F:  // BN4, BXI
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::BNX;
            iinf[RCAPX_NONE][ins].cycl = 2;
            iinf[RCAPX_NONE][ins].regnum = 4;
            inst[RCAPX_68][ins] = &CPU_RCA1802::BXI;
            iinf[RCAPX_68][ins].cycl = 3;
            break;
        case 0x60:  // INC reg X
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::INC;
            iinf[RCAPX_NONE][ins].regnum = X;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x68:  // Prefix
            if (support_1806) {
                inst[RCAPX_NONE][ins] = &CPU_RCA1802::Prefix;
                iinf[RCAPX_NONE][ins].cycl = 0;
            }
            break;
        case 0x70:  // RET
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::RET;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;      
        case 0x71:  // DIS
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::DIS;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;      
        case 0x72:  // LDA via X
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LDA;
            iinf[RCAPX_NONE][ins].regnum = X;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x73: // STXD Store via X and decrement
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::STXD;
            iinf[RCAPX_NONE][ins].regnum = X;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x74:  // ADC, DADC
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::ADC;
            iinf[RCAPX_NONE][ins].cycl = 2;
            inst[RCAPX_68][ins] = &CPU_RCA1802::DADC;
            iinf[RCAPX_68][ins].cycl = 4;
            break;      
        case 0x75:  // SDB
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SDB;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;      
        case 0x76:  // SHRC
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SHRC;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x77:  // SMB, DSMB
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SMB;
            iinf[RCAPX_NONE][ins].cycl = 2;
            inst[RCAPX_68][ins] = &CPU_RCA1802::DSMB;
            iinf[RCAPX_68][ins].cycl = 4;
            break;      
        case 0x78:  // SAV
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SAV;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;      
        case 0x79:  // MARK
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::MARK;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;      
        case 0x7A:  // REQ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::REQ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;      
        case 0x7B:  // SEQ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SEQ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;      
        case 0x7C:  // ADCI, DACI
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::ADCI;
            iinf[RCAPX_NONE][ins].cycl = 2;
            inst[RCAPX_68][ins] = &CPU_RCA1802::DACI;
            iinf[RCAPX_68][ins].cycl = 4;
            break;
        case 0x7D:  // SDBI
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SDBI;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x7E:  // SHLC
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SHLC;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0x7F:  // SMBI, DSBI
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SMBI;
            iinf[RCAPX_NONE][ins].cycl = 2;
            inst[RCAPX_68][ins] = &CPU_RCA1802::DSBI;
            iinf[RCAPX_68][ins].cycl = 4;
            break;      
        case 0xC0:  // LBR
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LBR;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xC1:  // LBQ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LBQ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xC2:  // LBZ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LBZ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xC3:  // LBDF
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LBDF;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xC4:  // NOP
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::NOP;
            iinf[RCAPX_NONE][ins].cycl = 3;
            break;
        case 0xC5:  // LSNQ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LSNQ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xC6:  // LSNZ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LSNZ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xC7:  // LSNF
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LSNF;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xC8:  // NLBR
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::NLBR;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xC9:  // LBNQ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LBNQ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xCA:  // LBNZ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LBNZ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xCB:  // LBNF also LSKP
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LBNF;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xCC:  // LSIE
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LSIE;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xCD:  // LSQ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LSQ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xCE:  // LSZ
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LSZ;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xCF:  // LSDF
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LSDF;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xF0:  // Load Via X       Memory pointed to by R(X) is loaded into D
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LDN;
            iinf[RCAPX_NONE][ins].regnum = X;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xF1:  // OR
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::OR;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xF2:  // AND
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::AND;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xF3:  // XOR
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::XOR;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xF4:  // ADD, DADD
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::ADD;
            iinf[RCAPX_NONE][ins].cycl = 2;
            inst[RCAPX_68][ins] = &CPU_RCA1802::DADD;
            iinf[RCAPX_68][ins].cycl = 4;
            break;      
        case 0xF5:  // SD
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SD;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;      
        case 0xF6:  // SHR
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SHR;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xF7:  // SM, DSM
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SM;
            iinf[RCAPX_NONE][ins].cycl = 2;
            inst[RCAPX_68][ins] = &CPU_RCA1802::DSM;
            iinf[RCAPX_68][ins].cycl = 4;
            break;      
        case 0xF8:  // LDI              Load immediate into D
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::LDI;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xF9:  // ORI
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::ORI;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xFA:  // ANI
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::ANI;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xFB:  // XRI
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::XRI;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xFC:  // ADI, DADI
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::ADI;
            iinf[RCAPX_NONE][ins].cycl = 2;
            inst[RCAPX_68][ins] = &CPU_RCA1802::DADI;
            iinf[RCAPX_68][ins].cycl = 4;
            break;      
        case 0xFD:  // SDI
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SDI;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;      
        case 0xFE:  // SHL
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SHL;
            iinf[RCAPX_NONE][ins].cycl = 2;
            break;
        case 0xFF:  // SMI, DSMI
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::SMI;
            iinf[RCAPX_NONE][ins].cycl = 2;
            inst[RCAPX_68][ins] = &CPU_RCA1802::DSMI;
            iinf[RCAPX_68][ins].cycl = 4;
            break;      
    }
    if (support_1806) {
        
    }
}

/*
        case 0x:    // 
            inst[RCAPX_NONE][ins] = &CPU_RCA1802::
            iinf[RCAPX_NONE][ins].regnum = 
            iinf[RCAPX_NONE][ins].cycl = 
            break;
*/

void CPU_RCA1802::hard_reset(void)
{
    cycles.left = 0;
    cycles.overage = 1; // Resetting takes 1 cycle
    Nlines = 0;
    counter.mode = RCACR_STOPPED;
    Q = 0;              // Q flipflop = 0
    XIE = 1;                // Enable interrupts
    MIE = 1;
    CIE = 1;
    counter.CIL = 0;
    counter.CNTR = 0;
    T = 0;
    IDL = false;
    IRQ = 0;
    X = 1;              // Default X
    P = 0;              // Default P
    DF = 0;
    curprefix = RCAPX_NONE;
    for (int i = 0; i < 16; i++)
    {
        R[i] = 0;
    }
}

void CPU_RCA1802::soft_reset(void)
{
    curprefix = RCAPX_NONE;
    cycles.left = 0;
    cycles.overage = 1; // Resetting takes 1 cycle
    Nlines = 0;
    Q = 0;              // Q flipflop = 0
    counter.mode = RCACR_STOPPED;
    XIE = 1;                // Enable interrupts
    MIE = 1;
    CIE = 1;
    counter.CIL = 0;
    IDL = false;
    IRQ = 0;
    T = ((X << 4) | (P & 0x0F));
    if (support_1806) X = 0;
    else X = 1;             // Default X
    P = 0;              // Default P
    R[0] = 0;
}


void CPU_RCA1802::IllegalOp(void)
{
}

void CPU_RCA1802::IllegalOpP(void)
{
}

// Idle 'til input
void CPU_RCA1802::iIDL(void)
{
    IDL = 1;
}

// LD Advance   Memory pointed to by R(N) is loaded into D, R(N)+1. DF is NOT changed.
void CPU_RCA1802::LDA(void)
{
    D = mem.read_mem8(this, R[N]);
    R[N]++;
}

// Load immediate into D
void CPU_RCA1802::LDI(void)
{
    D = mem.read_mem8(this, R[P]);
    R[P]++;
}

//  LD by N.    Memory pointed to by R(N) is loaded into D.
void CPU_RCA1802::LDN(void)
{
    D = mem.read_mem8(this, R[N]);
}

void CPU_RCA1802::STR(void)
{
    mem.write_mem8(this, R[N],D);
}

void CPU_RCA1802::STXD(void)
{
    mem.write_mem8(this, R[X],D);
    R[X]--;
}


void CPU_RCA1802::INC(void)
{
    R[N]++;
}

void CPU_RCA1802::DEC(void)
{
    R[N]--;
}


void CPU_RCA1802::NOP(void)
{
}

void CPU_RCA1802::GLO(void)
{
    D = (byte)(R[N] & 0xFF);
}

void CPU_RCA1802::GHI(void)
{
    D = (byte)((R[N] >> 8) & 0xFF);
}

void CPU_RCA1802::PLO(void)
{
    R[N] = (R[N] & 0xFF00) + (word)(D & 0xFF);
}

void CPU_RCA1802::PHI(void)
{
    R[N] = (R[N] & 0x00FF) + (((word)(D & 0xFF)) << 8);
}

void CPU_RCA1802::OR(void)
{
    D |= mem.read_mem8(this, R[X]);             // OR D with whatever's in memory at R[X]
}

void CPU_RCA1802::ORI(void)
{
    D |= mem.read_mem8(this, R[P]); // OR D with immediate data
    R[P]++;                 // Increment the program counter
}

void CPU_RCA1802::AND(void)
{
    D &= mem.read_mem8(this, R[X]);             // AND D with whatever's in memory at R[X]
}

void CPU_RCA1802::ANI(void)
{
    D &= mem.read_mem8(this, R[P]); // AND D with immediate data
    R[P]++;                 // Increment the program counter
}

void CPU_RCA1802::XOR(void)
{
    D ^= mem.read_mem8(this, R[X]);             // XOR D with whatever's in memory at R[X]
}

void CPU_RCA1802::XRI(void)
{
    D ^= mem.read_mem8(this, R[P]); // XOR D with immediate data
    R[P]++;                 // Increment the program counter
}

void CPU_RCA1802::SHL(void)
{
    if (D & 0x80) { DF = 1; } else { DF = 0; }
    D <<= 1;
}

void CPU_RCA1802::SHLC(void)    // Shift left with carry (rotate left)
{
    byte E;
    if (D & 0x80) { E = 1; } else { E = 0; }        // Get the MSB
    D <<= 1;                                        // Shift D left one
    D += (DF & 0x01);                               // Add in DF
    DF = E;                                         // Set DF to MSB
}

void CPU_RCA1802::SHR(void)
{
    DF = (D & 0x01);
    D >>= 1;
}

void CPU_RCA1802::SHRC(void)
{
    byte E = D & 0x01;  // Store the LSB
    D >>= 1;
    D += (DF << 7);     // Add in DF
    DF = E;             // Set DF
}

void CPU_RCA1802::ADD(void)
{
    byte foo = D;
    D += mem.read_mem8(this, R[X]);
    if (D < foo)    { DF = 1; } // Carry occured
    else            { DF = 0; } 
}

void CPU_RCA1802::ADI(void) // Add immediate
{
    byte foo = D;
    D += mem.read_mem8(this, R[P]);
    R[P]++;
    if (D < foo)    { DF = 1; } // Carry occured
    else            { DF = 0; } 
}

void CPU_RCA1802::ADC(void) // Add with carry
{
    word foo = (word)mem.read_mem8(this, R[X]) + (word)D + (word)DF;
    D = (byte)(foo & 0xFF);
    if (foo >= 0x100) DF = 1;
    else DF = 0;
}

void CPU_RCA1802::ADCI(void)    // Add immediate with carry
{
    word foo = (word)mem.read_mem8(this, R[P]) + (word)D + (word)DF;
    R[P]++;
    D = (byte)(foo & 0xFF);
    if (foo >= 0x100) DF = 1;
    else DF = 0;
}

void CPU_RCA1802::SD(void)
{
    byte op1 = mem.read_mem8(this, R[X]);
    byte op2 = D;
    D = op1 - op2;
    if (op1 >= op2)     { DF = 1; }         // No borrow
    else                { DF = 0; }         // Borrow
}

void CPU_RCA1802::SDI(void)
{
    byte op1 = mem.read_mem8(this, R[P]);
    R[P]++;
    byte op2 = D;
    D = op1 - op2;
    if (op1 >= op2)     { DF = 1; }         // No borrow
    else                { DF = 0; }         // Borrow
}

void CPU_RCA1802::SDB(void) // Subtract D with borrow
{
    int16 op1 = (int16)mem.read_mem8(this, R[X]);
    int16 op2 = (int16)D;
    int16 op3 = (int16)(1 - (DF & 0x01));

    D = (byte)op1 - (byte)op2 - (byte)op3;

    // Figure out if there was a borrow
    int16 op4 = op1 - op2 - op3;
    DF = ((op4 < 0) ? 0 : 1);           // Set borrow to 0 if there was, 1 if there wasn't
}

void CPU_RCA1802::SDBI(void)
{
    int16 op1 = (int16)mem.read_mem8(this, R[P]);
    R[P]++;
    int16 op2 = (int16)D;
    int16 op3 = (int16)(1 - (DF & 0x01));

    D = (byte)op1 - (byte)op2 - (byte)op3;

    // Figure out if there was a borrow
    int16 op4 = op1 - op2 - op3;
    DF = ((op4 < 0) ? 0 : 1);           // Set borrow to 0 if there was, 1 if there wasn't
}

void CPU_RCA1802::SM(void)
{
    byte op2 = mem.read_mem8(this, R[X]);
    byte op1 = D;
    D = op1 - op2;
    if (op1 >= op2)     { DF = 1; }         // No borrow
    else                { DF = 0; }         // Borrow
}

void CPU_RCA1802::SMI(void)
{
    byte op2 = mem.read_mem8(this, R[P]);
    R[P]++;
    byte op1 = D;
    D = op1 - op2;
    if (op1 >= op2)     { DF = 1; }         // No borrow
    else                { DF = 0; }         // Borrow
}

void CPU_RCA1802::SMB(void) // Subtract D with borrow
{
    int16 op2 = (int16)mem.read_mem8(this, R[X]);
    int16 op1 = (int16)D;
    int16 op3 = (int16)(1 - (DF & 0x01));

    D = (byte)op1 - (byte)op2 - (byte)op3;

    // Figure out if there was a borrow
    int16 op4 = op1 - op2 - op3;
    DF = ((op4 < 0) ? 0 : 1);           // Set borrow to 0 if there was, 1 if there wasn't
}

void CPU_RCA1802::SMBI(void)
{
    int16 op2 = (int16)mem.read_mem8(this, R[P]);
    R[P]++;
    int16 op1 = (int16)D;
    int16 op3 = (int16)(1 - (DF & 0x01));

    D = (byte)op1 - (byte)op2 - (byte)op3;

    // Figure out if there was a borrow
    int16 op4 = op1 - op2 - op3;
    DF = ((op4 < 0) ? 0 : 1);           // Set borrow to 0 if there was, 1 if there wasn't
}


void CPU_RCA1802::BR(void)
{
    R[P] = (R[P] & 0xFF00) + (word)mem.read_mem8(this, R[P]);
}

void CPU_RCA1802::NBR(void)
{
    R[P]++;
}

void CPU_RCA1802::BZ(void)
{
    R[P] = ((D == 0) ? ((word)mem.read_mem8(this, R[P]) + (R[P] & 0xFF00)) : (R[P]+1));
}

void CPU_RCA1802::BNZ(void)
{
    R[P] = ((D != 0) ? ((word)mem.read_mem8(this, R[P]) + (R[P] & 0xFF00)) : (R[P]+1));
}

void CPU_RCA1802::BDF(void)
{
    R[P] = ((DF == 1) ? ((word)mem.read_mem8(this, R[P]) + (R[P] & 0xFF00)) : (R[P]+1));
}

void CPU_RCA1802::BNF(void)
{
    R[P] = ((DF == 0) ? ((word)mem.read_mem8(this, R[P]) + (R[P] & 0xFF00)) : (R[P]+1));
}

void CPU_RCA1802::BQ(void)
{
    R[P] = ((Q == 1) ? ((word)mem.read_mem8(this, R[P]) + (R[P] & 0xFF00)) : (R[P]+1));
}

void CPU_RCA1802::BNQ(void)
{
    R[P] = ((Q == 0) ? ((word)mem.read_mem8(this, R[P]) + (R[P] & 0xFF00)) : (R[P]+1));
}

void CPU_RCA1802::BX(void)
{
    R[P] = ((read_EF(this, N) == 1) ? ((word)mem.read_mem8(this, R[P]) + (R[P] & 0xFF00)) : (R[P]+1));
}

void CPU_RCA1802::BNX(void)
{
    R[P] = ((read_EF(this, N) == 0) ? ((word)mem.read_mem8(this, R[P]) + (R[P] & 0xFF00)) : (R[P]+1));
}


void CPU_RCA1802::LBR(void)
{
    // High byte first, low byte second
    word yo = R[P];
    R[P] = (((word)mem.read_mem8(this, yo)) << 8) + ((word)mem.read_mem8(this, yo+1));
}

void CPU_RCA1802::NLBR(void)
{
    R[P] += 2;
}

void CPU_RCA1802::LBZ(void)
{
    word yo = R[P];
    R[P] = ((D == 0) ? ((((word)mem.read_mem8(this, yo)) << 8) + ((word)mem.read_mem8(this, yo+1))) : (R[P] + 2));
}

void CPU_RCA1802::LBNZ(void)
{
    word yo = R[P];
    R[P] = ((D != 0) ? ((((word)mem.read_mem8(this, yo)) << 8) + ((word)mem.read_mem8(this, yo+1))) : (R[P] + 2));
}

void CPU_RCA1802::LBDF(void)
{
    word yo = R[P];
    R[P] = ((DF == 1) ? ((((word)mem.read_mem8(this, yo)) << 8) + ((word)mem.read_mem8(this, yo+1))) : (R[P] + 2));
}

void CPU_RCA1802::LBNF(void)
{
    word yo = R[P];
    R[P] = ((DF == 0) ? ((((word)mem.read_mem8(this, yo)) << 8) + ((word)mem.read_mem8(this, yo+1))) : (R[P] + 2));
}

void CPU_RCA1802::LBQ(void)
{
    word yo = R[P];
    R[P] = ((Q == 1) ? ((((word)mem.read_mem8(this, yo)) << 8) + ((word)mem.read_mem8(this, yo+1))) : (R[P] + 2));
}

void CPU_RCA1802::LBNQ(void)
{
    word yo = R[P];
    R[P] = ((Q == 0) ? ((((word)mem.read_mem8(this, yo)) << 8) + ((word)mem.read_mem8(this, yo+1))) : (R[P] + 2));
}

void CPU_RCA1802::LSZ(void)
{
    if (D == 0) R[P] += 2;
}

void CPU_RCA1802::LSNZ(void)
{
    if (D != 0) R[P] += 2;
}

void CPU_RCA1802::LSDF(void)
{
    if (DF == 1) R[P] += 2;
}

void CPU_RCA1802::LSNF(void)
{
    if (DF == 0) R[P] += 2;
}

void CPU_RCA1802::LSQ(void)
{
    if (Q == 1) R[P] += 2;
}

void CPU_RCA1802::LSNQ(void)
{
    if (Q == 0) R[P] += 2;
}

void CPU_RCA1802::LSIE(void)
{
    if (MIE == 1) R[P] += 2;
}

void CPU_RCA1802::SEP(void)
{
    P = N;
}

void CPU_RCA1802::SEX(void)
{
    X = N;
}

void CPU_RCA1802::SEQ(void)
{
    this->write_Q(this,Q,1);
    Q = 1;
}

void CPU_RCA1802::REQ(void)
{
    this->write_Q(this,Q,0);
    Q = 0;
}

void CPU_RCA1802::SAV(void)
{
    mem.write_mem8(this, R[X],T);
}

void CPU_RCA1802::MARK(void)
{
    T = (X << 4) + (P & 0x0F);
    mem.write_mem8(this, R[2],T);
    X = P;
    R[2]--;
}

void CPU_RCA1802::RET(void)
{
    byte yo = mem.read_mem8(this, R[X]);
    X = (yo >> 4);
    P = (yo & 0x0F);
    R[X]++;
    MIE = 1;
}

void CPU_RCA1802::DIS(void)
{
    byte yo = mem.read_mem8(this, R[X]);
    X = (yo >> 4);
    P = (yo & 0x0F);
    R[X]++;
    MIE = 0;    
}

void CPU_RCA1802::INX(void)
{
    Nlines = N;
    byte Y = read_N(this,N);
    mem.write_mem8(this, R[X],Y);
    D = Y;
}

void CPU_RCA1802::OUTX(void)
{
    Nlines = N;
    write_N(this, N,mem.read_mem8(this, R[X]));
    R[X]++;
}


/***********************
 ** 1806 instructions **
 ***********************/
// This next one is basically an execute-next-instruction thingy
// It'll break if there's two 68's!
void CPU_RCA1802::Prefix()
{
    tcurins = 0x68;
    uint32 cadd = 0;
    // First we have to deal with the possability that there are multiple 0x68's
    do {
        R[P]++;                                     // Increment the PC
        byte tcurins = mem.read_mem8(this,R[P]);    // Get the current instruction
        cycles.left--;
        cycles.total++;
        cycles.since_call++;
        cadd++;
        if (cycles.left == 0) { R[P]--; iinf[0][0x68].cycl = 0; return; }   // If we run out of cycles, set the PC back one, and return
    } while(tcurins == 0x68);
    // Now execute the new instruction
    N = iinf[RCAPX_68][tcurins].regnum;         // Set N
    R[P]++;                                     // Increment the PC
    curprefix = RCAPX_68;
    (this->*inst[RCAPX_68][tcurins])();     // Call an instruction
    curprefix = RCAPX_NONE;
    iinf[RCAPX_NONE][curins].cycl = iinf[RCAPX_68][tcurins].cycl+cadd;
}

// Register load immediate
void CPU_RCA1802::RLDI(void)
{
    R[N] = (((word)mem.read_mem8(this,R[P])) << 8) | ((word)mem.read_mem8(this,R[P]+1));
    R[P]+=2;
}

// Register load via N and advance
void CPU_RCA1802::RLXA(void)
{
    R[N] = (((word)mem.read_mem8(this,R[X])) << 8) | ((word)mem.read_mem8(this,R[X]+1));
    R[X]+=2;
}

// Register store via X and decrement
void CPU_RCA1802::RSXD(void)
{
    mem.write_mem8(this,R[X],((byte)(R[N]&0xFF)));
    mem.write_mem8(this,R[X]-1,((byte)(R[N]>>8)));
    R[X]-=2;
    T = 0;
}

// Decrement reg N and long branch if not 0
void CPU_RCA1802::DBNZ(void)
{
    R[N]--;
    uint16 RP = R[P];
    if (R[N]==0) R[P]+=2;
    else R[P] = (((uint16)mem.read_mem8(this,RP))<<8) | ((uint16)mem.read_mem8(this,RP+1));
}

// Register N to Register X copy
void CPU_RCA1802::RNX(void)
{
    R[X] = R[N];
    T = 0;
}

// Decimal add
void CPU_RCA1802::DADD(void)
{
    byte o1lb = D & 0x0F;
    byte o1hb = D & 0xF0;
    //M(R(X)) + D
    byte o2 = mem.read_mem8(this,R[X]);
    byte o2lb = o2 & 0x0F;
    byte o2hb = o2 & 0xF0;

    o1lb &= 10;
    o1hb &= 10;
    o2lb &= 10;
    o2hb &= 10;

    byte lb = o1lb + o2lb;
    byte hb = o1hb + o2hb;

    DF = 0;
    if (lb >= 10) { lb -= 10; hb++; }
    if (hb >= 10) { hb -= 10; DF = 1; }
    D = lb | hb;
}

// Decimal add immediate
void CPU_RCA1802::DADI(void)
{
    byte o1lb = D & 0x0F;
    byte o1hb = D & 0xF0;
    //M(R(P)) + D
    byte o2 = mem.read_mem8(this,R[P]);
    R[P]++;
    byte o2lb = o2 & 0x0F;
    byte o2hb = o2 & 0xF0;

    o1lb &= 10;
    o1hb &= 10;
    o2lb &= 10;
    o2hb &= 10;

    byte lb = o1lb + o2lb;
    byte hb = o1hb + o2hb;

    DF = 0;
    if (lb >= 10) { lb -= 10; hb++; }
    if (hb >= 10) { hb -= 10; DF = 1; }
    D = lb | hb;
}

// Decimal add with carry
void CPU_RCA1802::DADC(void)
{
    byte o1lb = D & 0x0F;
    byte o1hb = D & 0xF0;
    //M(R(X)) + D
    byte o2 = mem.read_mem8(this,R[X]);
    byte o2lb = o2 & 0x0F;
    byte o2hb = o2 & 0xF0;

    o1lb &= 10;
    o1hb &= 10;
    o2lb &= 10;
    o2hb &= 10;

    o1lb += DF;

    byte lb = o1lb + o2lb;
    byte hb = o1hb + o2hb;

    DF = 0;
    if (lb >= 10) { lb -= 10; hb++; }
    if (hb >= 10) { hb -= 10; DF = 1; }
    D = lb | hb;
}

// Decimal add with carry, immediate
void CPU_RCA1802::DACI(void)
{
    byte o1lb = D & 0x0F;
    byte o1hb = D & 0xF0;
    //M(R(P)) + D
    byte o2 = mem.read_mem8(this,R[P]);
    R[P]++;
    byte o2lb = o2 & 0x0F;
    byte o2hb = o2 & 0xF0;

    o1lb &= 10;
    o1hb &= 10;
    o2lb &= 10;
    o2hb &= 10;
    o1lb += DF;

    byte lb = o1lb + o2lb;
    byte hb = o1hb + o2hb;

    DF = 0;
    if (lb >= 10) { lb -= 10; hb++; }
    if (hb >= 10) { hb -= 10; DF = 1; }
    D = lb | hb;
}

// Decimal subtract memory
void CPU_RCA1802::DSM(void)
{
}

// Decimal subract memory, immediate
void CPU_RCA1802::DSMI(void)
{
    R[P]++;
}

// Decimal subtract memory with borrow
void CPU_RCA1802::DSMB(void)
{
}

// Decimal subract memory with borrow immediate
void CPU_RCA1802::DSBI(void)
{
    R[P]++;
}

// Short branch on counter interrupt
void CPU_RCA1802::BCI(void)
{
    uint16 RP = R[P];
    if (counter.CIL==1) R[P] = (((word)mem.read_mem8(this,RP)) | (RP & 0xFF00));
    else R[P]++;
}

// Short branch on external interrupt
void CPU_RCA1802::BXI(void)
{
    uint16 RP = R[P];
    if (IRQ!=0) R[P] = (((word)mem.read_mem8(this,RP)) | (RP & 0xFF00));
    else R[P]++;
}

// Load counter
void CPU_RCA1802::LDC(void)
{
    if (counter.running == RCACR_STOPPED) { counter.CH = D; counter.CNTR = D; counter.CIL = 0; }
    else counter.CH = D;
}

// Get counter
void CPU_RCA1802::GEC(void)
{
    D = counter.CNTR;
}

// Stop counter
void CPU_RCA1802::STPC(void)
{
    counter.ps32 = 0;
    counter.running = RCACR_RUNNING;
}

// Decrement counter
void CPU_RCA1802::DTC(void)
{
    counter.CNTR--;
}

// Set timer mode and start (TPA / 32 -> counter)
void CPU_RCA1802::STM(void)
{
}

// Set counter mode 1 and start
void CPU_RCA1802::SCM1(void)
{
}

// Set counter mode 2 and start
void CPU_RCA1802::SCM2(void)
{
}

// Set pulse width mode 1 and start
void CPU_RCA1802::SPM1(void)
{
}

// Set pulse width mode 2 and start
void CPU_RCA1802::SPM2(void)
{
}

// Enable toggle Q
void CPU_RCA1802::ETQ(void)
{
}

// External interrupt enable
void CPU_RCA1802::sXIE(void)
{
    XIE = 1;
}

// External interrupt disable
void CPU_RCA1802::sXID(void)
{
    XIE = 0;
}

// Counter interrupt enable
void CPU_RCA1802::sCIE(void)
{
    CIE = 1;
}

// Counter interrupt disable
void CPU_RCA1802::sCID(void)
{
    CIE = 0;
}

// Save T, D, DF (note: previous T contents are destroyed)
void CPU_RCA1802::DSAV(void)
{
    R[X]--; mem.write_mem8(this,R[X],T);
    R[X]--; mem.write_mem8(this,R[X],D);
    R[X]--; D >>= 1; D += (DF << 7); mem.write_mem8(this,R[X],D);
    T = 0;
}

// Standard CALL
void CPU_RCA1802::SCAL(void)
{
    mem.write_mem8(this,R[X],(byte)(R[N]&0xFF));
    mem.write_mem8(this,R[X]-1,(byte)(R[N]>>8));
    R[X]-=2;
    R[N] = R[P];
    // M(R(N)) -> R(P).1
    // M(R(N)+1) -> R(P).0
    // R(N)+=2;
    R[P] = (((word)mem.read_mem8(this,R[N])) << 8) | ((word)mem.read_mem8(this,R[N]+1));
    R[N]+=2;
    T = 0;
}

// Standard return
void CPU_RCA1802::SRET(void)
{
    R[P] = R[N];
    R[N] = (((word)mem.read_mem8(this,R[X]+1)) << 8) | ((word)mem.read_mem8(this,R[X]+2));
    R[X]+=2;
    T = 0;
}

// Returns a string containing debug info dump
#define GETN (s->nextmem[0]&0x0F)
char *CPU_RCA1802::debug_str(CPU_RCA1802_DEBUG_STATE *s)
{
    char *ost = (char *)malloc(255);
    char *p;
    byte ins = s->nextmem[0];
    sprintf(ost,"                                                                                                                                                                                                                                                ");
    int eyo = 0;
    int yy = 0;
    switch(s->flag) {
    case CPU_STATE_RUNNING:
        sprintf(ost,"PC: %04X  I: %02X      ", s->s.R[s->s.P],s->nextmem[0]);
        p = ost+(strlen(ost));
        switch(ins&0xF0) {
        case 0x00:
            if (ins != 0) {
                sprintf(p,"LDN R%01X        ",GETN,s->s.R[GETN]);
                eyo = 1;
                yy = 1;
            }
            break;
        case 0x10:
            sprintf(p,"INC R%01X        ",GETN,GETN,s->s.R[GETN]);
            eyo = 1;
            yy = 1;
            break;
        case 0x20:
            sprintf(p,"DEC R%01X        ",GETN,GETN,s->s.R[GETN]);
            eyo = 1;
            yy = 1;
            break;
        case 0x40:
            sprintf(p,"LDA R%01X        ",GETN,s->s.R[GETN]);
            eyo = 1;
            yy = 1;
            break;
        case 0x50:
            sprintf(p,"STR R%01X        ",GETN,s->s.R[GETN]);
            eyo = 1;
            yy = 1;
            break;
        case 0x80:
            sprintf(p,"GLO R%01X        ",GETN,GETN,s->s.R[GETN]);
            eyo = 1;
            yy = 1;
            break;
        case 0x90:
            sprintf(p,"GHI R%01X        ",GETN,GETN,s->s.R[GETN]);
            eyo = 1;
            yy = 1;
            break;
        case 0xA0:
            sprintf(p,"PLO R%01X        ",GETN,GETN,s->s.R[GETN]);
            eyo = 1;
            yy = 1;
            break;
        case 0xB0:
            sprintf(p,"PHI R%01X        ",GETN,GETN,s->s.R[GETN]);
            eyo = 1;
            yy = 1;
            break;
        case 0xD0:
            sprintf(p,"SEP %01X     ",GETN);
            eyo = 1;
            break;
        case 0xE0:
            sprintf(p,"SEX %01X     ",GETN);
            eyo = 1;
            break;
        }

        switch(ins)
        {
        case 0x00:
            sprintf(p,"IDL      ");
            break;
        case 0x30:
            sprintf(p,"BR       ");
            break;
        case 0x32:
            sprintf(p,"BZ (D=0) ");
            break;
        case 0x33:
            sprintf(p,"BDF (DF=1)   ");
            break;
        case 0x36:
            sprintf(p,"B3 (EF3=1)   ");
            break;
        case 0x39:
            sprintf(p,"BNQ (Q!=1)   ");
            break;
        case 0x3A:
            sprintf(p,"BNZ (D!=0)   ");
            break;
        case 0x3B:
            sprintf(p,"BNF (DF=0)   ");
            break;
        case 0x61:
            sprintf(p,"OUT 1        ");
            break;
        case 0x62:
            sprintf(p,"OUT 2        ");
            break;
        case 0x63:
            sprintf(p,"OUT 3        ");
            break;
        case 0x64:
            sprintf(p,"OUT 4        ");
            break;
        case 0x65:
            sprintf(p,"OUT 5        ");
            break;
        case 0x66:
            sprintf(p,"OUT 6        ");
            break;
        case 0x67:
            sprintf(p,"OUT 7        ");
            break;
        case 0x69:
            sprintf(p,"INP 1        ");
            break;
        case 0x6A:
            sprintf(p,"INP 2        ");
            break;
        case 0x6B:
            sprintf(p,"INP 3        ");
            break;
        case 0x6C:
            sprintf(p,"INP 4        ");
            break;
        case 0x6D:
            sprintf(p,"INP 5        ");
            break;
        case 0x6E:
            sprintf(p,"INP 6        ");
            break;
        case 0x6F:
            sprintf(p,"INP 7        ");
            break;
        case 0x79:
            sprintf(p,"MARK         ");
            break;
        case 0x7B:
            sprintf(p,"SEQ          ");
            break;
        case 0xD4:
            sprintf(p,"SEP %01X     ",GETN);
            break;
        case 0xF3:
            sprintf(p,"XOR D,%04X   ",s->s.R[s->s.X]);
            break;
        case 0xF4:
            sprintf(p,"ADD D+%04X   ",s->s.R[s->s.X]);
            break;
        case 0xF6:
            sprintf(p,"SHR D        ");
            break;
        case 0xF8:
            sprintf(p,"LDI %02X     ",s->nextmem[1]);
            break;
        case 0xF9:
            sprintf(p,"ORI %02X     ",s->nextmem[1]);
            break;
        case 0xFA:
            sprintf(p,"ANI %02X     ",s->nextmem[1]);
            break;
        case 0xFB:
            sprintf(p,"XRI %02X     ",s->nextmem[1]);
            break;
        case 0xFC:
            sprintf(p,"ADI %02X     ",s->nextmem[1]);
            break;
        case 0xFF:
            sprintf(p,"SMI %02X     ",s->nextmem[1]);
            break;
        default:
            if (!eyo) sprintf(p,"UKN        ", s->nextmem[0]);
            break;
        }

        p = ost+(strlen(ost));
        //if (!yy) sprintf(p,"      DF:%02X D:%02X  RX[%01X]:%04X",s->s.DF, s->s.D,s->s.X,s->s.R[s->s.X]);
        //else sprintf(p,"DF:%02X   D:%02X  RX[%01X]:%04X",s->s.DF, s->s.D,s->s.X,s->s.R[s->s.X]);
        //if (!yy) sprintf(p,"DF:%02X   D:%02X  X:%01X  P:%01X",s->s.DF, s->s.D, s->s.X,s->s.P);
        //else sprintf(p,"DF:%02X   D:%02X  X:%01X  P:%01X",s->s.DF, s->s.D, s->s.X,s->s.P);
        sprintf(p,"DF:%02X  D:%02X  X:%01X  P:%01X  Next:%02X,%02X,%02X",s->s.DF, s->s.D, s->s.X,s->s.P,s->nextmem[1],s->nextmem[2],s->nextmem[3]);
        p = ost+(strlen(ost));
        sprintf(p,"\n                   R0:%04X  R1:%04X  R2:%04X  R3:%04X  R4:%04X  R5:%04X  R6:%04X  R7:%04X\n                    R8:%04X  R9:%04X  RA:%04X  RB:%04X  RC:%04X  RD:%04X RE:%04X  RF:%04X",s->s.R[0],s->s.R[1],s->s.R[2],s->s.R[3],s->s.R[4],s->s.R[5],s->s.R[6],s->s.R[7],s->s.R[8],s->s.R[9],s->s.R[10],s->s.R[11],s->s.R[12],s->s.R[13],s->s.R[14],s->s.R[15]);
        break;
    case CPU_STATE_STARTEDCYCLING:
        sprintf(ost,"Cycle() called");
        break;
    case CPU_STATE_STOPPEDCYCLING:
        sprintf(ost,"Cycle() exiting");
        break;
    case CPU_STATE_IDLING:
        sprintf(ost,"Idle state");
        break;
    case CPU_STATE_DMA:
        sprintf(ost,"DMA Request");
        break;
    case CPU_STATE_IRQ_EXECUTED:
        sprintf(ost,"IRQ Request");
        break;
    default:
        sprintf(ost,"Unknown state! %d", s->flag);
        break;
    }
    return ost;
}

---